A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge in a portion of the substrate. Each pixel cell has a readout circuit that includes at least an output field effect transistor formed on the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) selection of a pixel for readout; (4) resetting the storage region to a known state before the transfer of charge to it and output of an amplification of a signal representing the reset state; (5) transfer of charge to the storage region; and (6) output and amplification of a signal representing image charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The reset and image charge at the storage region is typically converted to a reset Vrst and image Vsig pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a portion of a conventional CMOS imager 10 employing a four transistor (4T) pixel 20. The illustrated imager 10 includes a pixel 20, one of many that are in a pixel array, connected to a column sample and hold circuit 40 by a column line 32. The imager 10 also includes a readout programmable gain amplifier (PGA) 70 and an analog-to-digital converter (ADC) 80.
The illustrated pixel 20 includes a photosensor 22 (e.g., a pinned photodiode, photogate, etc.), transfer transistor 24, floating diffusion region FD, reset transistor 26, source follower transistor 28 and row select transistor 30. The photosensor 22 is connected to the floating diffusion region FD by the transfer transistor 24 when the transfer transistor 24 is activated by a transfer control signal TX. The reset transistor 26 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa-pix. A reset control signal RST is used to activate the reset transistor 26, which resets the floating diffusion region FD prior to transfer of charge from the photosensor 22.
The source follower transistor 28 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa-pix and the row select transistor 30. The source follower transistor 28 converts the stored charge at the floating diffusion region FD into an electrical output voltage signal. The row select transistor 30 is controllable by a row select signal ROW_SELECT for selectively connecting the source follower transistor 28 and its output voltage signal to the column line 32.
The column sample and hold circuit 40 includes a current bias transistor 56, controlled by a control voltage signal VLN, that is used to bias the column line 32. The column line 32 is also connected to a first capacitor 44 thru a sample and hold reset signal switch 42. The sample and hold reset signal switch 42 is controlled by the sample and hold reset control signal S/H_RESET. The column line 32 is also connected to a second capacitor 54 thru a sample and hold pixel signal switch 52. The sample and hold pixel signal switch 52 is controlled by the sample and hold pixel control signal S/H_SIGNAL. The switches 42, 52 are typically MOSFET transistors.
A second terminal of the first capacitor 44 is connected to the amplifier 70 via a first column select switch 50, which is controlled by a column select signal COLUMN_SELECT. The second terminal of the first capacitor 44 is also connected to a clamping voltage VCL via a first clamping switch 46. Similarly, the second terminal of the second capacitor 54 is connected to the amplifier 70 by a second column select switch 60, which is controlled by the column select signal COLUMN_SELECT. The second terminal of the second capacitor 54 is also connected to the clamping voltage VCL by a second clamping switch 48. An equalizing switch 58 may also be optionally connected across the output sides of capacitors 44 and 54 to equalize the clamp voltage VCL applied to the two capacitors.
The clamping switches 46, 48 are controlled by a clamping control signal CLAMP. As is known in the art, the clamping voltage VCL is used to place a charge on the two capacitors 44, 54 before the reset and image output signals are stored on the capacitors 44, 54, respectively in response to sample and hold control signals S/H_RESET, S/H_SIGNAL.
Referring to FIGS. 1 and 2, in operation, the row select signal ROW_SELECT is driven high, which activates the row select transistor 30. When activated, the row select transistor 30 connects the source follower transistor 28 to the column line 32. The reset signal RST is then pulsed to activate the reset transistor 26, which resets the floating diffusion region FD. The signal on the floating diffusion region FD provides a reset output signal Vrst which is sampled when the sample and hold reset control signal S/H_RESET is pulsed. At this point, the first capacitor 44 stores the pixel reset signal Vrst.
Afterwards, the transfer transistor control signal TX is pulsed, causing charge from the photosensor 22 to be transferred to the floating diffusion region FD. The signal on the floating diffusion region FD provides an image signal Vsig which is sampled when the sample and hold pixel control signal S/H_SIGNAL is pulsed. At this point, the second capacitor 54 stores a pixel image signal Vsig. A differential signal (Vrst−Vsig) is produced by the differential amplifier 70. The differential signal is digitized by the analog-to-digital converter 80. The analog-to-digital converter 80 supplies the digitized pixel signals to an image processor (not shown), which forms a digital image output. Throughout the operation, the control voltage signal VLN, used to bias the column line 32, is maintained at a constant low level, causing a constant low current to flow through bias transistor 56.
A low current (iVLN) through bias transistor 56 is desired in order to increase the gain and uniformity in response of the source follower transistor 28. However, the capacitive time constant (τ) of the column line 32 depends on the capacity (CLN) of the column line 32 times the resistance (R) from the bias transistor 56, as expressed below in equation (1). The capacitive time constant (τ) is the exponential time constant for the circuit to reach a stable mode of operation. The resistance (R) is calculated as the voltage (v) divided by the current (iVLN). Lowering the current iVLN to maintain the desired effect on the source follower transistor 28, however, will increase the settling time, as shown below:
                    (                  τ          =                                                    C                                  L                  ⁢                                                                          ⁢                  N                                            ⁢              R                        =                                          C                                  L                  ⁢                                                                          ⁢                  N                                            ⁢                                                Δ                  ⁢                                                                          ⁢                  v                                                  i                                      VL                    ⁢                                                                                  ⁢                    N                                                                                      )                            (        1        )            
Accordingly, it is desired to decrease the capacitive time constant (τ) of the column line 32 while still maintaining a low current (iVLN) across the bias transistor 56 during charge sampling to maintain the desired gain and uniformity in the response of the source follower transistor 28. A decreased capacitive time constant (τ) will result in an improved row readout time, which is also desirable.